Field of the Invention
The present invention relates to a power factor correction circuit, and a power supply device using the same.
Description of Background Art
There has conventionally been known a voltage-doubler-type bridgeless power factor correction circuit which includes two capacitors connected in series and no diode bridge. One of the two capacitors stores power when a positive voltage is input, and the other stores power when a negative voltage is input. The voltage-doubler-type bridgeless power factor correction circuit can make a boosting ratio small by using the two capacitors connected in series. Further, since the voltage-doubler-type bridgeless power factor correction circuit does not include a diode bridge, a power loss can be reduced.
FIG. 18 is a circuit diagram of a voltage-doubler-type bridgeless power factor correction circuit described in Japanese Laid-Open Patent Publication No. 2012-19637. A power-factor correction circuit 9 shown in FIG. 18 includes a coil L1, FETs (Field Effect Transistors) T1, T2, diodes D1 to D4, and capacitors C1, C2. An AC power supply 7 is connected to the input side of the power factor correction circuit 9, and a load 8 is connected to the output side thereof.
When a positive voltage is input (when a potential at a first terminal of the AC power supply 7 (the upper-side terminal in the figure) is higher than a potential at the second terminal), the FET T1 is switched. When the FET T1 is in an on-state, energy is stored in the coil L1 When the FET T1 is in an off-state, the energy is released from the coil L1, and the capacitor C1 is charged with a boosted power. When a negative voltage is input (when the potential at the first terminal of the AC power supply 7 is lower than the potential at the second terminal), the FET T2 is switched. When the FET T2 is in the on-state, energy is stored in the coil L1. When the FET T2 is in the off-state, the energy is released from the coil L1, and the capacitor C2 is charged with the boosted power. The load 8 is supplied with the power from the capacitors C1, C2 connected in series. Hence the voltage applied to the load 8 is twice as large as the voltage generated by a boosting circuit including the coil L1 and the FET T1.
The power factor correction circuit 9 controls a duty ratio (a ratio of time when the FET is in the on-state in one period) of each of the FETs T1, T2 such that an input current is proportional to the input voltage, to correct a power factor. The power factor correction circuit 9 does not include a diode bridge made up of four diodes on the input side. Hence the power loss can be reduced when a current flows through the diodes. Further, the efficiency can be enhanced since the boosting ratio is one-naif as large as that of the typical boosting-type power factor correction circuit.
However, the power factor correction circuit 9 shown in FIG. 18 has a problem that when the range of the compatible input voltage (the output voltage of the AC power supply 7) is broadened, the output voltage (a DC voltage after boosting of the voltage) increases. This problem occurs, for example, when the power factor correction circuit 9 is made compatible with both a region with a commercial power supply voltage of 100 V and a region with that of 200 V.
In a boosting-type power factor correction circuit, which is not a double-boosting type and is usable in every country around the world (i.e., compatible with an input voltage of 100 V to 240 V), the output voltage is often around 400 V. It is assumed that the power factor correction circuit 9 is designed in line with the above, so that the output voltage is 400 V when the input voltage is 100 V (peak voltage is 141 V). In the power factor correction circuit 9 as thus designed, even with no boosting operation performed, the output voltage is 564 V when the input voltage is 200 V (peak voltage is 282 V), and the output voltage is 677 V when the input voltage is 240 V (peak voltage is 338 V).
As the output voltage is higher, components with higher withstand voltages are required, thus leading to increases in scale and cost of the power factor correction circuit. Further, the loss at the time of switching of a power element increases, thus leading to deterioration in efficiency of the power factor correction circuit.
The power factor correction circuit 9 shown in FIG. 18 requires the four diodes D1 to D4 of the diodes D1 to D4, the diodes D3, D4 mainly have the function of preventing a current from flowing backward. When a positive voltage is input, the diode D4 prevents a current from continuously flowing from the first terminal of the AC power supply 7 to the second terminal of the AC power supply 7 via a parasitic diode in the FET T2 and the coil L1. When a negative voltage is input, the diode D3 prevents a current from continuously flowing from the second terminal of the AC power supply 7 to the first terminal of the AC power supply 7 via the coil L1 and a parasitic diode in the FET T1.
The number of rectifier elements (diodes) included in the power factor correction circuit is preferably small. As the number of rectifier elements is smaller, the circuit can be further reduced in size and cost. Further, as the number of rectifier elements is smaller, the power loss can be further reduced when a current flows through the rectifier elements. From this point of view, the power factor correction circuit 9 shown in FIG. 18 has points to be improved.